Release History

2019.2.1 (May 15, 2019)


  • Tooltip and user guide on AC filter Frequency cutoff computation method have been updated
  • User inputs on evaluated design are now formatted into engineering notation

2019.2 (April 30, 2019)


MV-Drive applications

  • RLE Machine as an operating point for Integrated Motor Drive Designs has been added. Besides it supports for PLECS and PSIM exports for further product development
  • Moreover imposed LCR filter is now available for AC/DM Filter subsystem


  • New XLSX format for the design report
  • “Bill Of Materials” report has been included into the above-mentionned XLSX report


  • PLECS export is now available for NPC (module and discrete)
  • Heatsink design has been improved for more optimized results
  • Waveforms for the HV/DC and LV/AC sides of the converter circuit are now generated in 2 separate steps
  • Capacitor cost evaluation can now include a constant cost and a cost per rated voltage.
  • FEMM export has been improved and offers even more accurate outputs
  • Auto-design computation of winding resistance for parallelized “simple L model” inductors has been made even more accurate


  • Fixed a bug where the DC/DC LV filter auto-design algorithm would require an excessive capacitor rated voltage
  • Fixed a bug where inner ripple would not always be respected after AC filter design
  • Fixed a bug where 3D model would move when navigating inside an input

2019.1.2 (March 22, 2019)


  • Cooling design can now generate parallepipedic heatsinks
  • Better account for AC/LV filter design and modulation depth interdependance
  • Userguide has been reworked for improved clarity and now includes a better understanding of PowerForge’s way to compute powerswitch loss


  • Operating point has been moved from system-level to its own subsystem in order to consider different source / bus models (Motor, grid…) in the future
  • Only public references are now selected by default on newly created projects in order to avoid unwilling selections


  • Fixed a bug in inverter plecs computation
  • Fixed a bug in DC-DC LV inductor value design calculation for nPar=1
  • Fixed a bug in PLECS export on number types appearing in some use cases
  • Fixed a bug in PSIM export of NPC with MOSFET : clamp MOSFETs are now driven in reverse conduction
  • Fixed a bug on check voltage ripple referering to phase-to-phase voltage instead of phase-neutral voltage

2019.1 (February 07, 2019)


 Private references in library

  • Users can now create private discrete and module (leg, T-type, NPC) library references, providing loss data in Plecs XML format (‘Table only’ supported, no formula)
  • Users can now create private semiconductor package footprints (they can be used for abovementioned discretes & modules)
  • Private library references are shared among members of an organization
  • Private library references can be used interchangeably with public references in designs

  Project-specific library selection

  • Each project’s owner can select a freely-configurable subset of all available library references
  • Only selected library references will be used in the project’s designs


  • Semiconductor packages and frequency-domain limit lines (from conducted EMC standards) are now displayed as libraries
  • Library list views now feature pagination and full-text search
  • All libraries now offer a detail view for each reference
  • Voltage drop is now computed from a look-up-table instead of a simple linear (forward voltage + on-resistance) model
  • MOSFETs with external anti-parallel diodes are now supported, with proper reverse current split between MOSFET and diode chips in synchronous rectification
  • NPC inner switch turn-on events at zero current can now generate switching loss due to non-zero voltage: 1) outer switch is turned off, 2) clamp diode turns on, 3) opposite inner switch is turned on (as control signals with the outer switch are complementary) and sees its voltage fall from E/4 to 0
  • Exported PSIM circuit now include parasitic resistances in L and C elements
  • System-level “DC current” computation now takes into account the impact of AC filter loss – NB: minor change (typically 1%) introduced in patch release 2019.1.1 (February 25, 2019)
  • The project participant addition form now auto-suggests other organization members


  • Fixed computation of the EE inductor winding mass: window fill factor was taken into account twice
  • Fixed equivalent macrocell voltage spectrum shown for 3-phase AC L filters
  • Fixed computation of damping capacitor loss in DC LC filter with parallel RC damping
  • Fixed crash of thermal computation when both cooling and macrocell subsystems are in manual mode and use ‘unrealistic’ values
  • Fixed package names for 5SNA 0756650300 and 5SNA 0800J450300 references: ‘HiPak 1/2 HV’ replaced by ‘HiPak 1/2’
  • Fixed filter waveforms sometimes missing in manual mode
  • Fixed empty input field when using the same edition modal dialog twice
  • Fixed computation of flying capacitor mass, volume and cost for the SMC topology

2018.2 (September 25, 2018)


  New multilevel topologies

New bidirectional DC/AC multilevel topologies are offered:

  • 3-level Neutral Point Clamped (NPC) using NPC module
  • 3-level T-type using T-type module3-level T-type using discretes
  • Stacked MultiCell (multilevel SMC)

  PSIM export

Export ready-to-use files from simulation files and semiconductor loss data of the designed conversion stage.

  Cost estimation

This feature makes possible to estimate the cost of the converter (components + materials).

  Discretes and modules library viewer

A detailed view of the characteristics of discretes and modules (bridge leg, NPC & T-type) is now available from the library overview.


  Number of levels computed in the DC-AC case

The value displayed was referring to the phase-to-phase voltage and was wrong. It has been found it was much more relevant to display the number of levels of a waveform from one single phase leg.