Release History

2019.3.3 (Oct. 28, 2019)

BUG FIXES

  • Ratios for Mass × Rth and Volume × Rth on “Simple Rth” cooling models were incorrect and have been fixed
  • Fixed a bug where Tambient would be used instead of TcoldSource in “Simple Rth” cooling design
  • Fixed a bug where PLECS exports for DC-DC converters would sometimes compute losses wrongly
  • Added an error message when power switch temperatures are too high for design to be evaluated (> 1000°C)

IMPROVEMENTS

  • IAC THD, UAC THD and UAC Weighted THD are now available for all DC-AC designs
  • Added IAC THD as a new available filter and scatter plot axis
  • Improved overall application speed and reactivity

BEHAVIOUR CHANGES

  • AC power cannot be set to 0 to avoid errors and inaccuracies. This is meant to be improved at a later date.
2019.3.2 (Oct. 01, 2019)

NEW FEATURES

  • Magnetic loss curves are now available on magnetic materials details view

IMPROVEMENTS

  • Project and conversion stage steps have been merged to ease project setup
  • The choice between converter types (non-isolated DC/DC or 3-phase DC/AC) is now done at project creation
  • Once a project is created, designs can now be freely specified and evaluated without operating area restrictions
2019.3.1 (Sept. 16, 2019)

NEW FEATURES

Benchmark workspace overhaul
  • Custom scatter graphs can now be added in each project’s benchmark workspace
  • X and Y axis, as well as a color scale can be choosen among 10 design characteristics
  • All default scatter plots can be freely removed and replaced with new ones
  • Graphs are bound to the project
  • There’s no limit on how many graphs can be created
  • Designs in graphs can be filtered out by setting thresholdsvalues on choosen constraints
  • Filtered out designs are grayed out in scatter plots and bar graphs

BEHAVIOUR CHANGES

  • Powerswitch (IGBT and MOSFET SiC) losses have been reprocessed and now only reflects data from datasheets.
  • Default graphs have been replaced with new, removable graphs (X / Y / Color axis) :
    • Efficiency / Specific power / Switching frequency
    • Specific Power / Switching Frequency
    • Efficiency / Power Density / Number of levels
  • “Density Graphs” and “Comparison breakdown” have been renamed respectively to “Scatter plots” and “Subsystem comparison” to better reflect on their new contents.
  • File exports on design dashboard are now gathered in a single dropdown selector.

IMPROVEMENTS

Improvements on macrocell specification and reviewing in design dashboard
  • A max number of paralleliized switches can now be defined as a macrocell input
  • A new bar graph on powerswitch losses (with a breakdown conduction / switching) and junction temperatures (for both the transitor and the diode) has been added into macrocell subsystem view
Improvements on design selection for graphs
  • All graphs, including scatter plots, now only display designs that are selected for comparison
  • All graphs are now updated immediately after selection for comparison
  • All graphs are also updated live when a new design has been evaluating without the need to refresh the whole page
Improvements on powerswitch source data tracking
  • Source datasheet date and revision are now available on powerswitch detail view
  • Extraction method for loss data is now displayed wihtin respective graphs
Improvements on powerswitch source data tracking
  • Empty widgets (Such as 3D models and graphs) and result data tables have been removed from design dashboard when working on a draft
  • All data, including user inputs, are now displayed as data tables when reviewing design results
2019.3 (July 31, 2019)

NEW FEATURES

  • PLECS exports for T-Type and SMC topologies are now available
  • Simple C capacitor models for Flying Capacitor variants are now available
  • Switching frequency sweep
    • Allows to evaluate up to 20 designs per sweep by defining a range between two switching frequencies, and an increment
    • All designs generated by a sweep are now gathered in design groups
    • All plots for designs evaluated within the same sweep are now linked and identified by color in density graphs
    • Whole design groups are identified in density graphs with a legend and their visibility can be toggled
    • Whole design groups can now be selected for comparison breakdown or for deletion

BEHAVIOUR CHANGES

  • All designs evaluated manually are now stored in a “no group” group
  • Checkboxes for comparison are now replaced by an icon and are not visible if the comparison is not possible
  • When PSIM scripts are imported into PSIM, the script window is no longer prompt and the schematic file is automatically created. Note that these still need to be opened manually
  • Macrocell topologies have been renamed to now be homogeneous

IMPROVEMENTS

  • Design status on design list now auto-updates without refreshing the page
  • Design information and evaluation errors are now available next to the status of the design in the design list
  • “Compare selection” button on design list now displays the total number of selected designs
  • Density graphs and comparison breakdown are now split into two distinct tabs
  • Bars in comparison breakdown are now ordered following the design list order
  • Comments are now partially shown in the design selector on the design dashboard and can directly be edited through this window by clicking on the “Edit” button
  • Design results are now displayed in a tabular format for improved readability
  • Added design information when inductance current fluctuates under and over 0

BUG FIXES

  • Fixed a bug where the 3D model would not always react properly when cooler volume was set to 0
2019.2.3 (July 03, 2019)

NEW FEATURES

  • Data on design efficiency from 5% to 100% of its nominal power are now available as a downloadable CSV format
  • L Filter auto-design is now available for RLE machines

BEHAVIOUR CHANGES

  • “Specifications” part on conversion stage has been renamed “Operating area”
  • “In progress” status for non-evaluated designs has been renamed as “Draft”

IMPROVEMENTS

  • Current and voltage stress ratios for capacitors is now allowed over 100%
  • fsw / f0 ratios under 5 are now allowed (except when auto-designing a LC AC filter)
  • Used formula on AC/LV filters fCutoff tooltip has been updated for better understanding
  • Time to display component library contents has been optimized
  • “Warnings” have been renamed as “Design information” to better reflect on their contents
  • User roles have been renamed for improved clarity

BUG FIXES

  • Fixed a bug creating inaccuracies on APOD strategy when sample type was fixed to t0 or t1
  • Fixed a bug where displayed Ipk-pk on AC/LV filters schematics wouldn’t reflect on the correct value displayed in waveforms
  • Fixed a bug where displayed current ripple area on AC/LV filters wouldn’t be accurate
  • Fixed a bug where bottom cells in macrocell schematics would sometimes be incorrectly named
  • Fixed a bug where macrocell schematics tooltips would appear behind input fields
2019.2.1 (May 15, 2019)

IMPROVEMENTS

  • Tooltip and user guide on AC filter Frequency cut-off computation method have been updated
  • User inputs on evaluated design are now formatted into engineering notation
2019.2 (April 30, 2019)

NEW FEATURES

MV-Drive applications
  • RLE Machine as an operating point for Integrated Motor Drive Designs has been added. Besides it supports for PLECS and PSIM exports for further product development
  • Moreover imposed LCR filter is now available for AC/DM Filter subsystem

BEHAVIOUR CHANGES

  • New XLSX format for the design report
  • “Bill Of Materials” report has been included into the above-mentionned XLSX report

IMPROVEMENTS

  • PLECS export is now available for NPC (module and discrete)
  • Heatsink design has been improved for more optimized results
  • Waveforms for the HV/DC and LV/AC sides of the converter circuit are now generated in 2 separate steps
  • Capacitor cost evaluation can now include a constant cost and a cost per rated voltage.
  • FEMM export has been improved and offers even more accurate outputs
  • Auto-design computation of winding resistance for parallelized “simple L model” inductors has been made even more accurate

BUG FIXES

  • Fixed a bug where the DC/DC LV filter auto-design algorithm would require an excessive capacitor rated voltage
  • Fixed a bug where inner ripple would not always be respected after AC filter design
  • Fixed a bug where 3D model would move when navigating inside an input
2019.1.2 (March 22, 2019)

IMPROVEMENTS

  • Cooling design can now generate parallepipedic heatsinks
  • Better account for AC/LV filter design and modulation depth interdependance
  • Userguide has been reworked for improved clarity and now includes a better understanding of PowerForge’s way to compute powerswitch loss

BEHAVIOUR CHANGES

  • Operating point has been moved from system-level to its own subsystem in order to consider different source / bus models (Motor, grid…) in the future
  • Only public references are now selected by default on newly created projects in order to avoid unwilling selections

BUG FIXES

  • Fixed a bug in inverter plecs computation
  • Fixed a bug in DC-DC LV inductor value design calculation for nPar=1
  • Fixed a bug in PLECS export on number types appearing in some use cases
  • Fixed a bug in PSIM export of NPC with MOSFET : clamp MOSFETs are now driven in reverse conduction
  • Fixed a bug on check voltage ripple referering to phase-to-phase voltage instead of phase-neutral voltage
2019.1 (February 07, 2019)

NEW FEATURES

 Private references in library
  • Users can now create private discrete and module (leg, T-type, NPC) library references, providing loss data in Plecs XML format (‘Table only’ supported, no formula)
  • Users can now create private semiconductor package footprints (they can be used for abovementioned discretes & modules)
  • Private library references are shared among members of an organization
  • Private library references can be used interchangeably with public references in designs
  Project-specific library selection
  • Each project’s owner can select a freely-configurable subset of all available library references
  • Only selected library references will be used in the project’s designs

IMPROVEMENTS

  • Semiconductor packages and frequency-domain limit lines (from conducted EMC standards) are now displayed as libraries
  • Library list views now feature pagination and full-text search
  • All libraries now offer a detail view for each reference
  • Voltage drop is now computed from a look-up-table instead of a simple linear (forward voltage + on-resistance) model
  • MOSFETs with external anti-parallel diodes are now supported, with proper reverse current split between MOSFET and diode chips in synchronous rectification
  • NPC inner switch turn-on events at zero current can now generate switching loss due to non-zero voltage: 1) outer switch is turned off, 2) clamp diode turns on, 3) opposite inner switch is turned on (as control signals with the outer switch are complementary) and sees its voltage fall from E/4 to 0
  • Exported PSIM circuit now include parasitic resistances in L and C elements
  • System-level “DC current” computation now takes into account the impact of AC filter loss – NB: minor change (typically 1%) introduced in patch release 2019.1.1 (February 25, 2019)
  • The project participant addition form now auto-suggests other organization members

BUG FIXES

  • Fixed computation of the EE inductor winding mass: window fill factor was taken into account twice
  • Fixed equivalent macrocell voltage spectrum shown for 3-phase AC L filters
  • Fixed computation of damping capacitor loss in DC LC filter with parallel RC damping
  • Fixed crash of thermal computation when both cooling and macrocell subsystems are in manual mode and use ‘unrealistic’ values
  • Fixed package names for 5SNA 0756650300 and 5SNA 0800J450300 references: ‘HiPak 1/2 HV’ replaced by ‘HiPak 1/2’
  • Fixed filter waveforms sometimes missing in manual mode
  • Fixed empty input field when using the same edition modal dialog twice
  • Fixed computation of flying capacitor mass, volume and cost for the SMC topology
2018.2 (Sept. 25, 2019)

NEW FEATURES

  New multilevel topologies

New bidirectional DC/AC multilevel topologies are offered:

  • 3-level Neutral Point Clamped (NPC) using NPC module
  • 3-level T-type using T-type module3-level T-type using discretes
  • Stacked MultiCell (multilevel SMC)

  PSIM export

Export ready-to-use files from simulation files and semiconductor loss data of the designed conversion stage.

  Cost estimation

This feature makes possible to estimate the cost of the converter (components + materials).

  Discretes and modules library viewer

A detailed view of the characteristics of discretes and modules (bridge leg, NPC & T-type) is now available from the library overview.

BUG FIXES

  Number of levels computed in the DC-AC case

The value displayed was referring to the phase-to-phase voltage and was wrong. It has been found it was much more relevant to display the number of levels of a waveform from one single phase leg.